Tilera Launches 64-Core Embedded Processor

MIT Spin-out creates 64-core processor based on "mesh" architecture

Tilera Corporation, 2004 MIT startup founded on proof-of-concept mesh-based computing today launched the TILE64 processor. TILE64 is the first in a family of Tile Processor chips based on am architecture that can scale to hundreds and even thousands of cores.

TILE64 Processor Block Diagram (Source: Tilera)

However, don't get too excited while dreaming of 64-core gaming. Tilera claims the TILE64 has potential uses in video processing and network applications, but the processor is designed more as 64 systems on a single chip, rather than a 64-core general purpose GPU.

"This is the first significant new development in chip architecture in a decade," said Tilera President and CEO, Devesh Garg. "We developed this new architecture because existing multicore technologies simply cannot scale beyond a handful of cores. Moreover, customers have repeatedly indicated that the current multicore software tools are very primitive because they are based on single-processor-core models. We're introducing a revolutionary hardware and software platform that has solved the fundamental challenges associated with multicore scalability."

Tilera's new architecture eliminates the on-chip bus interconnect by placing a communications switch on each processor core and arranging them in a grid fashion on the chip, which the company calls iMesh -- intelligent Mesh.

Instead of a dedicated socket interface, the TILE64 daughterboard plugs into standard PCIe. A host operating system -- Linux or Windows -- recognizes the daughterboard as a new device instead of an extra 64 CPUs.

Each of the tiles is a full-featured, general-purpose processor that includes L1 and L2 caches, as well as a distributed L3 cache. Each core is also capable of running its own operating system, such as Linux. The cores can then interact with the iMesh network, which provides extremely low-latency, high bandwidth communications between the cores, memory and the I/O.

Intel's Teraflops Research Chip carries a striking resemblence to TILE64. Indeed, Tilera and Intel even carry the same terminology to describe the tiles and their functionality. In theory, both chips behave almost identically with regard to mesh computing -- one tile or several tiles can be confgured to act in parallel.

In order to minimize total system power, cost and footprint, the TILE64 processor integrates four DDR2 memory controllers and a complete array of high speed I/O interfaces; including two 10 Gbps XAUI, two 10 Gbps PCIe, two 1 Gbps Ethernet RGMII and a programmable flexible I/O interface to support interfaces such as compact flash and disk drives.

Each core consumes approximately 170 to 300 milliwatts. While each core does not reside on a separate power plane individual cores can be set into deep sleep states. However even with this aggressive sleep state management, the process is still fabricated entirely on TSMC's aging (and relatively inefficient) 90nm node; the company has not announced plans to shrink this process technology.

Intel's Teraflops Research Chip boasts nearly two teraFLOPs of processing power on a single 80-core processor, TILE64 musters about a tenth of that. However, aside from the fact that Tilera's CPU is available today, the focus for TILE64 is high performance-per-watt, as evidenced by its sub-20 watt peak-load envelope.

The processor is ideally suited for high performance embedded system markets, such as switches, security appliances and high-definition video applications. Tilera claims the chip will be available today in 600MHz to 900MHz variants, though corporate documentation (PDF) suggests 1GHz models exist but are not commercially available. Production pricing for the TILE64-family starts at $435 in bulk quantities.

Tilera's roadmap also includes plans for a 36-core and a 120-core device.

Taken from http://www.dailytech.com